The present invention relates to a channel apparatus used in a data processing system, and in particular to a channel apparatus for improving the data transfer speed between a main storage and an I/O device, as well as a computer system using it.
FIG. 1 shows the construction of a conventional channel apparatus (which may be called an I/O device in a broad sense). In the figure, a channel apparatus (IOP) 6 consists of a channel processor (CHP) 20 and a channel cluster (CCL) 24. The CHP 20 interfaces with a central processing unit (CPU) 2 through a line 100 and with a main storage (MS) 4 through a line 101. The CCL 24 interfaces with I/O devices 8-0 to 8-7. The CCL 24 has 8 channels CH0-CH7. Since the different channels have the same construction, only the construction of the channel CH0 is indicated in FIG. 1 in detail and details of the construction of the other channels CH1-CH7 are omitted therein. Hereinbelow the channel CH0 will be explained.
The channel CH0 communicates with the CHP 20 through a line 200. A control section 50 executes a microprogram (.mu.P) to control the operation of the channel CH0 and to start a transfer control section 70. In this way data transfer is started. The control section 50 sets a transfer count in a transfer counter 60 through a line 210 in units of bytes. When transfer is terminated, the transfer control section 70 informs the control section 50 of the termination. Data is transferred between an I/O device 8 and the MS 4 through a data buffer (CBS) 30. Data transfer between the CBS 30 and the MS 4 is effected in units of a block, one data block consisting of 32 bytes. The address of a data block to be transferred on the MS 4 is held by a block address register (BAR) 27. The initial value of the BAR 27 is set by the control section 50 through a line 220. The address held by the BAR 20 is incremented by 1 by an adder 40, every time one data block is transferred. The BAR 27 holds the upper 26 bits as a block address obtained by excluding the least significant 5 bits from the 31 bits of an address for addressing a data block on the MS 4. Consequently the adder 40 adds "1" to the least significant bit of a block address held by the BAR 27. A serial/parallel converting circuit 80 and an opto-electric converting circuit 81 are disposed between the CBS 30 and the I/O device 8. Data is transferred through an optical fiber cable 300 in bit serial form through the serial/parallel converting circuit 80 and opto-electric converting circuit 81. The frame of data transferred through the optical fiber cable 300 is described in, for example, "Enterprise Systems Architecture/390 ESCON I/O Interface (SA22-7202)" pp. 3-2.about.3-3, 6-6, published by IBM Corporation in the US. In the I/O device 8 there are disposed a channel port 61 and a storage unit 63. The channel port 61 is connected with the optical fiber cable 300 and transfers data between the channel apparatus and the I/O device.
The throughput requirement of an I/O device, e.g., an auxiliary storage device, connected with the channel apparatus increases every year. In contrast to the fact that the throughput of a channel widely utilized in practice for a large scale general purpose computer is at most 17 MB/s, a throughput greater than 100 MB/s is made possible in an auxiliary storage device called a disk array in which disk drives are disposed in parallel to transfer data in parallel. Further, LANs (Local Area Network) having a data transfer speed of an order of 1 Gbps are now available on the market. An HIPPI (High Performance Parallel Interface) channel based on the ANSI standards can be cited as a means for connecting such a high speed I/O device with a large scale computer. On the other hand, taking compatibility with a conventional device into account, there would be considered a channel apparatus in which only the transfer speed is increased with little modification of the above conventional channel interface. However, this approach requires use of high speed optical modules in a transmitter-receiver system for a channel in order to increase the transfer speed, using the serial transfer system as it is, which gives rise in many cases to a problem that the cost therefor is extremely increased. Further, it was necessary to change the control clock for each of the transmitter-receiver systems in the conventional device, which gives rise to a problem that the amount of change in design will be great.
As a method for solving these problems it has been proposed to dispose a plurality of channels in parallel, which channels are operated simultaneously, as described in JP-A-64-7243 and JP-A-3-58156. JP-A-64-7243 discloses a computer having channels and a main storage of interleave structure, in which computer the channels and banks of the main storage are directly connected through a dedicated parallel channel control device so that data can be transferred in parallel between the main storage and the channels. However this method can not always be used in a computer in which a secondary cache is provided between the channels and the main storage. Further, since in general a main storage device and a secondary cache device have a throughput which is extremely greater than that of a channel, it is necessary to be conscious of the need for the interleave structure to small in at most several channels disposed in parallel. In JP-A-3-58156 a plurality of channels are arranged in parallel in units of bytes and a request is issued in units of bytes. In a computer system, in which a request is issued to the main storage device in a unit of a value greater than 1 byte, e.g., 32 bytes, even when a structure of parallel channels is employed, it requires an extremely great amount of change in hardware to enable a request to be issued in units of bytes.